1. Field of the Invention
The present invention relates to a time constant calibration circuit, and more particularly, to a time constant calibration circuit and related method utilizing an analog adjusting mechanism for adjusting a capacitor or a current source.
2. Description of the Prior Art
Filters are generally needed in many communication transmission application circuits. Because the variability of an R.C. filter is smaller than that of a gmC filter, the R.C. filter is widely used as it is more easily controlled when designed. However, RC components have errors due to process variations, causing the actual time constant value to differ from a preset (desired) value, which further affects performance of the circuit and accuracy of the frequency response. For those cases without calibration included, the difference between the actual value and preset value is up to ±30%-50% (depending on the types of capacitors and resistors used); and such a great frequency response offset in the circuit is unacceptable for circuits demanding accurate frequency response.
To handle the time constant errors caused by process variations, many circuits and methods suitable for automatic frequency calibration are developed. Please refer to FIG. 1. FIG. 1 is a circuit diagram illustrating a conventional time constant calibration device 100. As shown in FIG. 1, the time constant calibration device 100 comprises a first voltage generating circuit 110, a second voltage generating circuit 120, and a comparing circuit 130. The first voltage generating circuit 110 comprises a clock signal generator 112, a constant current source 114 for providing a constant current Ic, and a switching-capacitor circuit 140. The switching-capacitor circuit 140 comprises a first capacitive component C1, which is a variable capacitive component (e.g., a varactor), a first switch component 142, a second switch component 143, a second capacitive component Cs1, and a third switch component 145. The clock signal generator 112 respectively generates a first clock signal ψ1 and a second clock signal ψ2, where the first clock signal ψ1 and the second clock signal ψ2 are non-overlapped to each other and are utilized for driving the switching-capacitor circuit 140 to generate a first voltage Vc. The second voltage generating circuit 120 comprises a differential circuit 122, a constant current source 123 for providing a constant current Ic, a transistor 124 and another constant current source 125 for providing a constant current K*Ic passing through a resistive component to generate a second voltage Vr. The comparing circuit 130 comprises a comparator 132 and a digital logic 134, where the comparator 132 compares the second voltage Vr with a bandgap reference voltage Vref to generate a comparing signal. The comparing circuit 130 then sends the comparing signal to the digital logic 134 for generating a digital control code to turn on/off each capacitor unit, thereby further adjusting the final capacitance value of the capacitor C1. It should be noted that related art needs a bandgap reference voltage circuit for generating the needed bandgap reference voltage Vref. However, as the bandgap reference voltage circuit has be widely used for different application fields for providing a stable reference voltage within a temperature range, and operations and functions of the bandgap reference voltage circuit are well known to those skilled in the art, further description is omitted here for brevity.
Please note that an objective of the conventional time constant calibration device 100 is to maintain a fixed time constant R1*C1 by adjusting the variable capacitor C1. Simply described, an operational principle of the conventional time constant calibration device 100 can be represented using two formulas. First, from the view of the second voltage generating circuit 120, the second voltage Vr is Vr−K*Ic*R1, and compared with the bandgap reference voltage Vref, the second voltage Vr in steady state is Vref=K*Ic*R1. Second, from the view of the first voltage generating circuit 110, the clock signal generator 112 generates the first clock signal ψ1 and the second clock signal ψ2 respectively, where the first clock signal ψ1 and the second clock signal ψ2 with a period T are non-overlapped to each other and are used for driving the switching-capacitor circuit 140, and thus generates a first voltage Vc.
Therefore, when the constant current Ic charges the capacitor C1 in one period T, the first voltage Vc generated by the capacitance C1 is represented by: Vc=Ic*T/(2C1). When the clock signal allows the capacitor C1 to discharge, the second capacitive component Cs1 maintains the first voltage Vc, and when Vc=Vref, an equation R1*C1=T/2K is obtained. Because both T and K are known constants, the RC time constant therefore is an invariant value. The control method of the circuit is utilizing the comparator 132 for generating a digital control code to turn on/off each capacitor unit, thereby adjusting the final capacitance value of the capacitor C1. However, a circuit utilizing the digital control code to adjust the final capacitance value needs to design quite a large number of branches of capacitor units with corresponding switches if high resolution is demanded. As a result, applying a capacitance multiplication technique to such a circuit is improper.
However, system on chip (SoC) has become mainstream for IC designs and phase lock loop (PLL) or PLL-based applications are indispensable for SoC. As known to those skilled in this art, as the manufacturing process of CMOS (Complementary Metal-Oxide-Semiconductor) improves, the chip areas of transistors are reduced, except for passive components inside the chip. A low pass filter, consisting of resistor(s) and capacitor(s), is part of the PLL. The low pass filters are always disposed outside the chip for reducing chip area and saving production costs in the past few years. To meet the trend of SoC design nowadays, low pass filters are merged into chips while these passive components still occupy most of the chip area. Therefore how to reduce the area of theses passive components has become an important topic of IC design.